eeprom理论及制造技术.doc

EEPROM Te chnology ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING CMOS P rocess Variations EEPROM F abrication Technology Dr. Lynn F uller Webpage: /lffeee Micro electro nic Engineering Ro chester Institute of Techno lo gy 82 Lomb Memo rial Drive Ro chester, NY 14623-5604 Tel (585) 475-2035 Email: Lynn.Fuller@ Department Webpage: http://www. micro e. rit. edu Rochester Institute of Technology Microelectronic Engineering 2-22-2012 EEPROM.PPT ? February 22, 2012 Dr. Lynn Fuller, Professor Page 1 EEPROM Te chnology OUTLINE Introduction Tunneling Gate Oxide EEPROM Programming Reading Test Specification/Results Fowler-Nordheim Tunneling Process Variation Tunnel Oxide Recipe Test Chip Layout Step-by-Step Process Rochester Institute of Technology Microelectronic Engineering ? February 22, 2012 Dr. Lynn Fuller, Professor Page 2 EEPROM Te chnology INTRODUCTION In certain applications, data mus t be electrically entered a nd erased from Read Onl y Memor y (ROM). The procedure can involve the enti re ROM sections or one memor y cell at a ti me. From the various technol ogi es available, we have chosen the design of a FLOTOX EEPROM ( FLOati ng- gate Tunnel i ng Oxi de ElectricallyErasable Programmable ROM, Fi gure 1. Thi s EEPROM cell ha s double polysilicon gates, with the top polysilicon as the control gate a nd the lower polysilicon as the fl oati ng gate. A thi n tunnel i ng oxi de is for med above the drain in the FLOTOX Transi stor. Rochester Institute of Technology Microelectronic Engineering ? February 22, 2012 Dr. Lynn Fuller, Professor Page 3 EEPROM Te chnology TUNNELING GATE OXIDE EEPROM Another form of the FLOTOX Tra nsistor is shown below. The structure is simpler and smaller but is more difficult to manufacture because of the problems associated with diffusion of phosphorous from the gate poly through the tunnel oxide into the transistor channel region. Most modern EEPROM devices use this structure. Sourc e Gate Drain n+ n+ P-we ll or P substra