3dictsv介绍与工艺流程.docxVIP

Chapter 7 Introduction to 3D Integration Technology using TSV Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline ? Why 3D Integration ? An Exemplary TSV Process Flow ? Stacking Strategies ? Concept of 3D IC Design ? Summary Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 IC Technology Evolution Chip Single-chip package Printed board Chemical Bio Sensors Other Sensors, Imagers 3D-SIP Nano Device MEMS RF ADC DAC Memory Stack Processor 3D-IC Energy/Power Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU Why 3D Integration ? Integrating more and more transistors in a single chip to support more and more powerful functionality is a trend ? Using 2D integration technology to implement such complex chips is more and more expensive and difficult ? Some alternative technologies attempting to cope with the bottlenecks of 2D integration technology have been proposed ? 3D integration technology using through silicon via (TSV) has been acknowledged as one of the future chip design technologies Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 3D Integration Technology Using TSV ? 3D integration technology using TSV ? Multiple dies are stacked and TSV is used for the inter-die interconnection Die 1 Die 2 Die 3 TSV ? The fabrication flow of a 3D IC ? Die/wafer preparation ? Die/wafer assembly Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 What is TSV ? Through Silicon Via (TSV): ? A via that goes through the silicon substrate ? Used for dies stacking Top Bump Al wiring TSV Wiring layer CMOS Diameter 50 um or less Via made by laser SiO2 insulator Top Bump ? Typical TSV technologies ? Via-first, via-middle, and via-last technologies Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 Via-First TSV Technology ? Via-First TSV (1) Before CMOS (2) After CMOS BEOL Source: Yole, 2007. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 Via-Last TSV Technology ? Via-L