PowerPoint Presentation - Efficient Dynamic Verification :PowerPoint演示文稿的高效动态验证.pptVIP

PowerPoint Presentation - Efficient Dynamic Verification :PowerPoint演示文稿的高效动态验证.ppt

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* * * no processor can do all kinds of computation efficiently. For a variety of reasons, acquisition cost should not exceed $200M and the annual operating power cost should not exceed $20M, which limits the power to 20 MW Power wall, cpu is not efficient for all the kinds of computation. No one device can do every computation in an efficient way DARPA study identify four challenge for exascale computing : 1) energy and power challenge 2) memory and storage challenge 3) concurrency and locality challenge 4) resiliency challenge number one issue is energy will not be a practical path to exascale computing a heterogeneous mix of distinct scalar and vector units. o the efforts of NVIDIA and their industry partners. Intels ongoing plans for its Many Integrated Core (MIC) co-processor and AMDs introduction of its CPU-GPU Fusion processors are yet additional indications that the industry is moving to an architecture where trade-off between flexibility / programmability / genericity and efficiency as important as ever today, with transformation of Moore’s Law from speed-based to concurrency-based, due to power considerations One interpretation of “Amdalh’s law” ? We will always need powerful, general purpose cores to speed up sequential parts of our applications! “Future processors will be a mix of general purpose and specialized cores” For this paper, I will mainly talk about the programmability and efficiency, and mainly about how to schedule SPMD computation on heterhgonesou cluster * There is also the scalablity issue but didn’t have much discuss in this presentatoin. ; multi-core, coprocessor, accelerator, are heterogeneous architecture Accelerator are attached to gpu with pci-e bus Programmability is another issue * These programming models very different from each other because they are designed for different devices, To make the parallel program for these heterogenesou devices you can Either use a hybrid programming model, or use a uniform programming

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