文件采用0 13μmcmos96通道全数据速率直接神经接口.pdfVIP

文件采用0 13μmcmos96通道全数据速率直接神经接口.pdf

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14-2 A 96-Channel Full Data Rate Direct Neural Interface in 0.13μm CMOS 1 1 1 2 1 1 1 Ross M. Walker , Hua Gao , Paul Nuyujukian , Kofi Makinwa , K. V. Shenoy , Teresa Meng , Boris Murmann 1Stanford University, Stanford, CA 94305, USA, 2Delft University of Technology, Delft, Th herlands from a significant noise penalty due to foldback from sampling. A power and area efficien sor interface consumes 6.5 mW from 1.2 V s while occupying 5 mm x 5 mm in 0.13 µm CMOS. The interface enables full bandwidth access to 96 channels of data acquired from cortical microelectrodes as part of a head-mounted wireless recording system for unconstrained primate neuroscience experiments. Open loop amplification and switched-capacitor (SC) filtering with 2.2 µVrms input referred noise conditions the signals before conversion by 10-bit SAR ADCs with 60.3 dB SNDR and 41.5 fJ/conv step. Introduction Acquisition of extracellular neural action potentials (ENAP) and local field potentials (LFP) from cortical brain regions is an important application of low-power mixed-signal IC systems, enabling basic neuroscience research as well as emerging clinical . Research tools created by IC designers are used by scientists in exploring the function of the central and peripheral nervous systems [1-4], and make an impact in the way we diagnose, treat, and understand a broad range of neurological ailments such as epilepsy, chronic

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