同步FIFO的Verilog代码(最新整理版).docxVIP

同步FIFO的Verilog代码 í???FIFOμ?Verilog?ú?? module fifo_syn(datain, rd, wr, rst, clk, dataout, full, empty); input [7:0] datain; input rd, wr, rst, clk; output [7:0] dataout; output full, empty; reg [7:0] dataout; reg full_in, empty_in; reg [7:0] mem [15:0]; reg [3:0] rp, wp; assign full = full_in; assign empty = empty_in; // memory read out é?×?DT?? always@(posedge clk) begin if(rd ~empty_in) dataout = mem[rp]; end end // memory write in always@(posedge clk) begin if(wr ~full_in) mem[wp]=datain; end // memory write pointer increment always@(posedge clk or negedge rst) if(!rst) wp=0; else wp = (wr ~full_in) ? (wp + 1b1) : wp; // memory read pointer increment always@(posedge clk or negedge rst) if(!rst) rp = 0; else rp = (rd ~empty_in)? (rp + 1b1): rp; // Full signal generate always@(posedge clk or negedge rst) begin if(!rst) full_in = 1b0; else begin if( (~rd wr)((wp==rp-1) | | (rp==4h0wp==4hf))) full_in = 1b1; else if(full_in rd) full_in = 1b0; end // Empty signal generate always@(posedge clk or negedge rst) begin if(!rst) empty_in = 1b1; else begin if((rd~wr)(rp==wp-1 || (rp==4hfwp==4h0))) empty_in=1b1; else if(empty_in wr) empty_in=1b0; end end endmodule ******************************************************************** *********** í?é?μ??ú???áêy?Yê???(dataout)??????êü?áê??ü(rd)????????è????????ùò?é ?×?DT??????ó ,?ú?à ******************************************************************** ************ ****** áíò???????μ?í???FIFO module FIFO_Buffer( Data_out, stack_full, stack_almost_full, stack_half_full, stack_almost_empty, stack_empty, Data_in, write_to_stack, read_from_stack, clk,rst ); parameter stack_width=32; parameter stack_height=8; parameter stack_ptr_width=3; parameter AE_level=2; parameter AF_level=6; parameter HF_level=4; output [stack_width-1:0] Data_out; output stack_full,stack_almost_full,stack_half_full; output stack_almost_empty,stack_empty; input[stack_width-1:0] Data_in; input writ