第7章IO接口技术-DMA-8237.pptVIP

Chapter 7?Homework 3、6、7、10、11、12 15、16、19、21、25 ◆ Compression?read mode:?block transfer, only the?S2?and?S4?are two?clocks,?time signals and?write?signals?are?generated?in the?S4?state,?for high-speed?circuits. ◆ Extended?writing?(write?ahead): S2, S3, S4?three states, but his writing?is?generated when?the signal?S3,?the purpose?is to use?the?falling edge?trigger?READY?signal to the low-speed?I / O?timing?is still?not complete?in the general?read and write,?Insert?wait state SW.  Above two methods?can be?carried out?in the?manner?set?control word. Channel?Register ： Base address register （16bits）： ?Storage? start address of memory. Current?Address Register （16bits）：Store?the?current address?being accessed , Each?byte ?by?sending that address add?1or minus?1?. Base?byte counter （16bits）: Stored?the number of bytes?of data block?(to keep). Current byte?counter (16 bits): Each?byte that is transferred?by?1until?reduced to?0, producing?an end?signal?EOP. Mode?register?(6?bits): Set the??work style of channel. Request?bit (1):??when?the software? request DAM?transfer? is 1. “ Mask bit?(1?bit):?when it is ?1“ the?channel request?is masked 。 6、The function of?internal registers?of 8237 Public?Registers(command?status) ： Command?register (8 bits):?control operation?mode (write) Status register?(8?bits):?storage of?state information?(read) Temporary register(8bits):?storage?memory?to?memory?data?transmission Before?/ after?trigger?(1):??control?the 16-bit ?read and write register of?the high?and low?byte 0: read, write?low byte??1: read, write?high byte Note:?the implementation of?a read?or write operation?automatically switches. Lord shield: port assignments of 8237: A3A2A1A0 register 0 0 0 0?? Address Register of Channel 0 0 0 0 1? ?Byte counter?of channel 00 0 1 0? ?Address Register of Channel 1 0 0 1 1? ?Byte counter of Channel 1 0 1 0 0? ?Address Register of Channel 2 0 1 0 1? Byte?counter of channel 20 1 1 0? Address Regis