数字电子技术(课件)lec16.pptVIP

* Chapter 7 Latches, Flip-Flops, and Timers * Logic Diagram for a Basic J-K Flip-Flop with Active-LOW Preset and Clear Inputs Lecture 16: FF Evolution and Application Preset and Clear can not be low at the same time. * Chapter 7 Latches, Flip-Flops, and Timers * Test your understanding Lecture 16: FF Evolution and Application Q is initially in 0 state. What kind of connection for J, K input? Ans: toggle connection. What type of triggering for clock pulse? Ans: rise edge triggering. Preset Toggle Clear * Chapter 7 Latches, Flip-Flops, and Timers * 74AHC74 Dual Positive Edge-Triggered D Flip-Flop It is a CMOS device. Two identical D_FFs share the VDD and ground. Lecture 16: FF Evolution and Application * Chapter 7 Latches, Flip-Flops, and Timers * 74HC112 dual negative edge-triggered J-K flip-flop Lecture 16: FF Evolution and Application Falling edge triggering * Chapter 7 Latches, Flip-Flops, and Timers * Test Your Understanding The 1J, 1K, 1CLK, 1PRE, and 1CLR waveforms are applied to 74HC112, determine the 1Q output. Lecture 16: FF Evolution and Application * Chapter 7 Latches, Flip-Flops, and Timers * Flip-Flop Operating Characteristics 1. Propagation delay times It is the time required after an input signal has been applied for the resulting output change to occur. Four categories of propagation delay times are important in the operation of a FF: tPLH as measured from the triggering edge of the clock pulse. tPHL as measured from the triggering edge of the clock pulse. tPLH as measured from the leading edge of the preset input. tPHL as measured from the leading edge of the clear input. Lecture 16: FF Evolution and Application * Chapter 7 Latches, Flip-Flops, and Timers * Pictures Showing Propagation Delays Propagation delays, clock to output Preset input to output and Clear input to output Lecture 16: FF Evolution and Application * Chapter 7 Latches, Flip-Flops, and Timers * Flip-Flop Operating Characteristics 2. Set-up time ts It is the minimum interva