《EDA技术实用教程(第四版)》习题答案.doc

《EDA技术》习题习 题 画出与以下实体描述对应的原理图符号元件: ENTITY buf3s IS --实体1:三态缓冲器 PORT(input:IN STD_LOGIC; --输入端 enable:IN STD_LOGIC; --使能端 output:OUT STD_LOGIC); --输出端 END buf3s ; ENTITY mux21 IS --实体2: 2选1多路选择器 PORT(in0, in1,sel: IN STD_LOGIC; output:OUT STD_LOGIC); 3-2 图-16所示的是4选1多路选择器,试分别用IF_THEN语句和CASE语句的表达方式写出此电路的VHDL程序,选择控制信号s1和s0的数据类型为STD_LOGIC_VECTOR;当s1=’0’,s0=’0’s1=’0’,s0=’1’；s1=’1’,s0=’0’和s1=’1’,s0=’1’时,分别执行y=a、y=b、y=c、y=d。 用IF_THEN语句 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41 IS PORT (a,b,c,d: IN STD_LOGIC; s0: IN STD_LOGIC; s1: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY mux41; ARCHITECTURE if_mux41 OF mux41 IS SIGNAL s0s1 : STD_LOGIC_VECTOR(1 DOWNTO 0);--定义标准逻辑位矢量数据 BEGIN s0s1=s1s0; --s1相并s0,即s1与s0并置操作 PROCESS(s0s1,a,b,c,d) BEGIN IF s0s1 = 00 THEN y = a; ELSIF s0s1 = 01 THEN y = b; ELSIF s0s1 = 10 THEN y = c; ELSE y = d; END IF; END PROCESS; END ARCHITECTURE if_mux41; --解2：用CASE语句4选1多路选择器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41 IS PORT (a,b,c,d: IN STD_LOGIC; s0: IN STD_LOGIC; s1: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY mux41; ARCHITECTURE case_mux41 OF mux41 IS SIGNAL s0s1 : STD_LOGIC_VECTOR(1 DOWNTO 0);--定义标准逻辑位矢量数据类型 BEGIN s0s1=s1s0; --s1相并s0,即s1与s0并置操作 PROCESS(s0s1,a,b,c,d) BEGIN CASE s0s1 IS --类似于真值表的case语句 WHEN 00 = y = a; WHEN 01 = y = b; WHEN 10 = y = c; WHEN 11 = y = d; WHEN OTHERS =NULL ; END CASE; END PROCESS; END ARCHITECTURE case_mux41; 3-3 图-17所示的是双2选1多路选择器构成的电路MUXK,对于其中MUX21A,当s=’’和s=’’时,分别有y=‘a’和y=’b’。试在一个结构体中用两个进程来表达此电路,每个进程中用CASE语句描