补充1 一般时序逻辑电路及状态机设计VHDL.pptVIP

一般时序逻辑电路及状态机的设计 常见电路： 1、触发器电路（D、T、RS、JK等） 2、寄存器电路 3、计数器电路 4、典型Moore型状态机 5、典型Mealy型状态机 例1：T触发器设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tff1 is port (clk: in std_logic; q: out std_logic); end; architecture aaa of tff1 is signal q_n: std_logic; begin process(clk) begin if rising_edge(clk) then q_n=not q_n; end if; end process; q=q_n; end; 例2：RS触发设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity rs_ff is port (r,s,qn: in std_logic; qn1: out std_logic); end; architecture aaa of rs_ff is begin process(r,s,qn) begin if (r and s)=0 then qn1=s or (not r and qn); end if; end process; end; 例3：JK触发器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity jk_ff is port (j,k,qn,clk: in std_logic; qn1: out std_logic); end; architecture aaa of jk_ff is begin process(j,k,qn,clk) begin if rising_edge(clk) then qn1=(not qn and j) or (not k and qn); end if; end process; end; 例4：D触发器设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity d_ff is port (d,clk,reset: in std_logic; q,qb: out std_logic); end; architecture aaa of d_ff is begin process(clk,reset) begin if (reset=1) then q=0; qb=1; elsif rising_edge(clk) then q=d; qb=not d; end if; end process; end; 三态缓冲器 从理论上说，用VHDL描述三态缓冲器的实现方法有很多种，但实际上各种综合器对三态缓冲器的描述都有比较严格的要求，下面是默认的两种描述方式： library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tribuffer1 is port (oe: in std_logic; datain: in std_logic; dataout: out std_logic ); end; architecture tristate of trib