VLSI设计基本流程课件.pptVIP

P* VHDL设计状态机实例 Moor型状态机 library ieee; use ieee.std_logic_1164.all; entity moore is port(clk, rst:in std_logic; id:in std_logic_vector(3 downto 0); y:out std_logic_vector(1 downto 0)); end moore; architecture archmoore2 of moore is Signal state: std_logic_vector(2 downto 0); constant state0: std_logic_vector(2 downto 0) := 000; constant state1: std_logic_vector(2 downto 0) := 010; constant state2: std_logic_vector(2 downto 0) := 011; constant state3: std_logic_vector(2 downto 0) := 110; constant state4: std_logic_vector(2 downto 0) := 111;------------