毕业设计（论文）-基于FPGA的数字幅频均衡功率放大器--硬件电路设计.docVIP

数字幅频均衡功率放大器 ——硬件电路设计 摘要 本文设计了一个基于FPGA的数字信号处理技术的幅频均衡功率放大器（硬件电路）。系统由前置放大器、低通滤波、带阻网络、AD转换、FPGA数字幅频均衡、DA转换及功率放大电路构成。 前置放大是采用运放NE5532设计的同相比例放大电路，实现了500倍的电压放大，通频带为20hz-20khz，输出电阻为600欧；无源T型带阻滤波器的中心频率是10kHz，衰减为-11.735db；AD转换电路采用16位，转换速率250ksps的ADS8505芯片，在FPGA设计一个数字幅频参数均衡器,补偿前级带阻网络的频响特性，以达到幅频均衡的目的，通频带20hz-20KHz内的电压幅度波动在1.5db以内。数字幅频均衡后的信号通过DAC5687（采样率500ksps）转换，并在OCL低频功放电路驱动负载，OCL功率放大电路输出功率大于10W，转换效率大于50%。基本实现题目要求。 关键字：数字幅频均衡；功率放大器；前置放大；带阻滤波器；ADC;DAC； Digital Amplitude-Frequency Balanced Power Amplifier ——Circuit Design This thesis is to design a digital amplitude-frequency balanced amplifier by digital signal processing technology on FPGA .?The system is consists of pre-amplifier, low pass filter, band-stop network, A / D sampling, FPGA digital amplitude and frequency equalization circuit, DA conversion and power amplification circuit.?Preamplifier is a circuit which Amplifier with the phase ratio consists by NE5532, voltage of 500-fold magnification, when the pass band attenuation -0.56db as 20hz-20khz, output resistance is 600 ohm. The center frequency of passive band-stop filter is 10kHz, the attenuation -11.735db, after sampling the output signal through the AD, in the FPGA ,the design of a digital amplitude and frequency parameters of the equalizer to compensate the former level frequency response characteristics of band-stop networks to achieve the objective of balanced amplitude and frequency - pass band 20hz-20KHz range of the voltage fluctuations within the 1.5db.? DA sampling the signal by digital amplitude-frequency balanced into the OCL low-frequency power amplifier circuit and driving the load.?The OCL power amplifier circuit output power of 12.6W, conversion efficiency of 65%.?This amplifier can better handle the signal to achieve power amplification Keywords: digital amplitude-frequency equalization; Power Amplifier; Preamplifier; Bandstop filter;A/D; 目 录 第一章 绪 论 5 1.1 引言 5 1.2 数字幅频均衡功率放大器的优点与应用 5 1.3 本课题的研究任务和论文介绍 6 1.31 设计的主要任务 6 1.32 论文的主要内容 6