基于VHDL语言组合逻辑电路设计.docVIP

基于VHDL语言组合逻辑电路设计 摘要 随着EDA技术的发展与应用,引起了电子产品开发的革命性变革。电子工程技术人员利用先进的EDA工具,基于VHDL硬件描述语言,借助FPGA进行系统级数字逻辑电路的设计与实现,越来越广泛地运用在电子工业领域。本文通过应用实例探讨硬件描述语言VHDL的知识要点和学习难点,针对几种典型的组合逻辑电路采用不同的设计方案 Abstract Along with the development of the technology and application of EDA, caused the electronic product development the revolutionary transformation. Electronic engineering and technical personnel the use of advanced EDA tools, hardware description language based on VHDL, with the FPGA digital logic circuit system level for the design and implementation of more and more widely used in electronic industry. This article through the application example discussion hardware description language knowledge points and study of VHDL difficulty, according to several kinds of typical assembly logic circuit using different design scheme 设计内容 八选一选择器： 真值表： a g y 000 0 d0 001 0 d1 010 0 d2 011 0 d3 100 0 d4 101 0 d5 110 0 d6 111 0 d7 a）源程序 library ieee; use ieee.std_logic_1164.all; entity mux8_1 is port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic; g:in std_logic; a:in std_logic_vector(2 downto 0); y:out std_logic); end entity mux8_1; architecture one of mux8_1 is begin process(a,g,d0,d1,d2,d3,d4,d5,d6,d7) begin if g=0then y=0; else case a is when000=y=d0; when001=y=d1; when010=y=d2; when011=y=d3; when100=y=d4; when101=y=d5; when110=y=d6; when111=y=d7; when others=y=0; end case; end if; end process; end architecture one; b)电路图 c)波形图 （2）8-3编码器： 真值表： in0 in1 In2 in3 in4 in5 in6 in7 输出 0 0 0 0 0 0 0 1 111 0 0 0 0 0 0 1 0 110 0 0 0 0 0 1 0 0 101 0 0 0 0 1 0 0 0 100 0 0 0 1 0 0 0 0 011 0 0 1 0 0 0 0 0 010 0 1 0 0 0 0 0 0 001 1 0 0 0 0 0 0 0 000 a）源程序 library ieee; use ieee.std_logic_1164.all; entity bianmaqi is port(input:in std_logic_vector(7 downto 0); output:out std_logic_vector(2 downto 0)); end entity; architecture art of bianmaqi is begin output=111 when input(7)=1 else 110 when input(6)=1 e