Noise Canceling in 1-D Data Presentation #13.ppt

FPAdder Updates Both simulations work ? No more weird funky outputs FPAdder1: ExtractedRC Simulations Results Project Description What does the chip do? It is part of the a research done by a CMU Robotics faculty How does it fit in the big picture Why did we find this interesting Marketing Potential Medical/ robotic applications Rehabilitation/ human-computer interfaces Vehicle maneuvering Hearing aid Computer devices applications ** can be implemented in other applications Behavioral/ Algorithmic Description How the top level works Communications between toplevel modules Datapath (Block Diagram) Input/Output Design Process Research done in CMU (want to implement the software into hardware Main target : to have optimum power saving feature Design tradeoffs between different implementation of major blocks Decision based on design goals (worked in parallel) C code / Behavioral Verilog / Structrural Verilog Schematics / Layout Floorplan Evolution All the steps that we went through Verification Process Codes Schematics Layout Timing Issues Encountered Floating point numbers (too small) Issues for major modules Adders Multipliers DFFs Timing issues Signal strength Ways to solve the problems Chip Specification Physical properties Size/ Dimension Transistor count Area/ density Pin-outs Throughput Frequency Pin specs Inputs/outputs/constants Descriptions Part specs Major blocks properties Layout Layout masks Poly Metal 1 Metal 2 Metal 3 Metal 4 Full chip layout Final floorplan with final chip Conclusion Summary of projects Improvements in future Importance of optimization/ good floor planning/ team communication * * Noise Canceling in 1-D Data: Presentation #13 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 April 20th, 2005 Short Final Presentation Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer Status Design proposal (Done) Architecture propo