Analog to Digital Converters.ppt

Analog to Digital Converters Conversion Principles Performance Limitations 1 Performance Limitations 2 Parallel or Flash ADCs Sub-Ranging ADCs Folding ADCs Folding Processor Successive Approx. ADCs DAC Realization 1 DAC Realization 2 DAC Realization 3 DAC Realization 4 DAC Realization 5 DAC8 with Unity-Gain Amplifier DAC Realization 6 Current Cell Floor Plan DAC Implementation Modified SA Algorithm 1 Modified SA Algorithm 2 SC Implementation Timing Diagram Offset Compensated Circuit Building Blocks 1 Building Blocks 2 Layout of 8-Bit ADC Spice Simulation (Bsim3) Pipelined ADCs Integrating or Serial ADCs SC Dual-Slope ADC ADC Testing Performance Metrics 1 Performance Metrics 2 ADC Error Sources Static Errors Element or Ratio Mismatches Finite Op-amp Gain Op-amp Comparator Offsets Deviations of Reference Dynamic Errors Finite (Amplifier) Bandwidth Op-amp Comparator Slew Rate Clock Feed-through Noise (Resistors, Op-amps, switched Capacitors) Intermodulation Products (Signal and Clock) Static Testing Dynamic Testing Histogram or Code-Density Test Histogram Test Simulated Histogram Test FFT Test Simulated FFT Test 10-Bit Dual-Slope ADC Types of Tests Static Testing Dynamic Testing In static testing, the input varies slowly to reveal the actual code transitions. ? Yields INL, DNL, Gain and Offset Error. Dynamic testing shows the response of the circuit to rapidly changing signals. This reveals settling errors and other dynamic effects such as inter-modulation products, clock-feed-trough, etc. Circuit Under Test Output Input Clock Error Types Offset Gain DNL INL Missing Codes IDEAL ADC Static Errors Frequency Domain Characterization Ideal n-Bit ADC: SNR = 6.02 x n + 1.76 [dB] fsig Amplitude Servo-loop Technique Comparator, integrator, and ADC under test are in negative feedback loop to determine the analog signal level required for every digital code transition. Integrator output represents equivalent a