Performance and Power Analysis of Timemultiplexed Execution on Dynamically Reconfigurable.pdfVIP

Performance and Power Analysis of Time-multiplexed Execution on Dynamically Reconfigurable Processor 1 1 1 1 Yohei Hasegawa , Shohei Abe , Shunsuke Kurotaki , Vu Manh Tuan , 1 2 2 2 Naohiro Katsura , Takuro Nakamura , Takashi Nishimura and Hideharu Amano 1 Graduate School of Science and Technology, Keio University 2 Faculty of Science and Technology, Keio University 3-14-1 Hiyoshi, Kouhoku-ku, Yokohama, 223-8522 Japan drp@am.ics.keio.ac.jp Abstract tion of power dissipation become a significant challenge because of wide spread of battery-powered devices. The Dynamically Reconfigurable Processor (DRP) devel- strong growth of wireless communications and portable ap- oped by NEC Electronics is a coarse grain reconfigurable plications is also a remarkable factor behind this trend. So, processor that selects a datapath called a context from the the power efficient architecture must be examined for future on-chip repository of sixteen circuit configurations at run- embedded systems. time. The time-multiplexed execution based on the multi- The most remarkable characteristic of dynamically re- context functionality is expected to drastically improve area configurable processors is the dynamic reconfigurability and power efficiency. To demonstrate the impact of the time- based on the multicontext functionality. The