《Wire_Speed_Presentation_5.5_-_Final4》.pdfVIP

5.5 A Wire-Speed PowerTM Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads Charles Johnson, David H. Allen, Jeff Brown, Steve Vanderwiel, Russ Hoover, Heather Achilles, Chen-Yong Cher, George A. May, Hubertus Franke, Jimi Xenidis, Claude Basso IBM Research System Technology Group 1 Wire-Speed Processor: Goals • Address new evolving market • Address performance issues relating to “new” semiconductor scaling properties • Reduced application power requirements – Achieve 50% thru Architecture – Achieve 50% thru Implementation 2 Wire-Speed Processor Technology IBM 45nm SOI Core Frequency 2.3GHz @ 0.97V (Worst Case Process) Chip size 428 mm2 (including kerf) Chip Power (4-AT node) 65W @ 2.0GHz, 0.85V Max Single Chip Chip Power (1-AT node) 20W @ 1.4GHz, 0.77V Min Single Chip Main Voltage (VDD) 0.7V to 1.1V Metal Layers 11 Cu (3-1x, 2-1.3x, 3-2x, 1-4x, 2-10x) Latch Count 3.2M Transistor Count 1.43B A2 Cores / Threads 16 / 64 L1 I D Cache 16 x (16KB + 16KB) SRAM L2 Cache 4 x 2MB eDRAM Hardware Accelerators Crypto, Compression, RegX, XML Intelligent Network Host Ethernet Adapter/Packet Processor Interfaces 2 Modes: Endpoint Network 2x DDR3 controllers Memory Bandwidth 4 Channels @ 800-1600MHz System I/O Bandwidth 4x 10G Ethernet, 2x PCI Gen2 Chip-to-Chip Bandwidth 3 Links, 20GB/s per link Chip Scaling 4 Chip SMP Package 50mm FCPBGA (4 or 6 layers