基于FPGA的高速AD采样设计.pdfVIP

20 10 1 20 10 No. 1 2 0 10 2 AERO W EAPONRY Feb. 2010 FPGA AD 齐红涛, 苏 涛 (西安电子科技大学雷达信号处理国家重点实验室, 西安 7 10071) : 随着雷达技术及现代宽带通信技术的发展, 高速ADC在数字化宽带接收器的设计 起了重要作用本文提出基于 FPGA 的高速AD 采样设计, 给出了基于 FPGA 的高速采样时钟设 计方案以及 FPGA 对时钟芯片 AD9516_4与ADC 的配置设置, 并对采样结果有效位数进行测定 结果证明该设计灵活简单通用性强 : FPGA; 高速AD; AD9516_4有效位数 : TN911. 7 : A : 1673- 5048( 2010) 0 1- 0035- 05 Design ofHighAD SamplingBased onFPGA Q IHon -tao, SU tao ( NationalK ey Lab of Radar S i nal Processin , X idian Un ivers ity, X i. an 71007 1, Ch ina) Abstract: A lon w ith the developm ent of the technolo y of radar and modernw ide band commun ica- tions, h i h ADC p layed an mi portant role in the desi n of di italw ide band receiver. This paper ives a desi n of h i h AD samplin based on FPGA, the hi h samplin clock based on FPGA and the confi ured chips ofAD9516_4 and ADC by FPGA. Effective Number O f Bits( ENOB) of the samplin result are measured. The result show s that the desi n is flex ib le, smi ple and enera-l purpose. Keywords: FPGA; H i h-speed AD; AD9516_4 ENOB , DSP 0 , 1 , ADC[ 1] , FPGA AD9516_4ADC , ADC [ 3] 400 M , FPGA A ltera Stratix Ò [ 2] EP2S60F1020 LVDS , ADC, A tmel 8 ADC , LVDS 640 AT 84AD001, ADC AD9516_4 M S / sADC FPGA FPGA ADC , LVDS, , ADC FPGA ADC AD9516 _ 4