MOSSequentiallogicI.pptVIP

Characterizing Timing Register Latch C2Q with respect to clock, D2Q to input signal Maximum Clock Frequency Also another constraint: tcd,reg + tcd,logic =thold tcd: contamination delay = minimum delay This constraint ensures the input data of the sequential circuits is held long enough after the clock edge and not modified too soon by the new coming-in data tc2q + tp,comb + tsetup = T Clock period T must accommodate the longest possible delay Positive Feedback: Bi-Stability V i 1 A C B V o 2 V i 1 = V o 2 V o1 Vi2 V i 2 = V o 1 When the gain of inverter in transient region is larger than 1, A B are the only stable operating points, C is metastable. Meta-Stability Gain should be larger than 1 in the transition region Hence, cross coupling of two inverters results in a bistable circuit, that is a circuit with two stable states. The circuit serves as a memory, storing either a 1 or 0 (A or B) Bistable circuit In absence of triggering, a bistable circuit remains in a single state (static memory as long as power is on). Another common name for a bistable circuit is flip-flop A FF is only useful when there is a mean to bring it from one state to the other one. Two approaches can achieve that: cutting the feedback loop, once the feedback loop is open, a new value can be written. This is called multiplexer based. Overpowering the feedback loop, by applying a trigger signal at the input of the FF, a new value is forced into the circuit by overpowering the previous stored value. Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0 D Q 0 CLK 1 D Q Out2 should remain at VDD since Out1 transitions to 0 during evaluation. However, since there is a finite propagation delay for the input to discharge Out1 to GND, the second output also starts to discharge. The second dynamic inverter turns off (PDN) when Out1 reaches VTn. Setting all inputs of the second gate to 0 during precharge will fix it.