microarchitectural techniques to reduce interconnect power in.pptVIP

University of Utah University of Utah Oct 31st 2007 University of Utah * Multi-Cores: Architecture/VLSI Perspective The Hardware-Software Relationship: Date or Dump? Embedded Applications --Spencer From discreet cochlear implants to high-end biomedical imaging! Multi-cores speed up performance by 50x! Creating new application domains! How to use “multiple” cores? Oct 31st 2007 * Parallel programming Synchronization Deadlock Livelock Memory management Oct 31st 2007 * How to use “multiple” cores? Program = Communication + Computation Global restructuring and parallelization Oct 31st 2007 * Structured “Communication” Lang: StreamIt, MPI Compilers: RAW, CoGenE Architecture: TRIPS, HWRT Key: Help other levels and leverage communication Another Constraint? Oct 31st 2007 * Parallel programming Synchronization Deadlock Livelock Memory management Hey.. Surprise!!! Communication Scheduling Another Constraint? Oct 31st 2007 * Oh God!!! Communication Scheduling Focus of Architecture Research Reduce the load of programmers Hardware transactional memory Aggressive pre-fetching Dynamic reconfiguration at every possible level Keep the architectural innovations transparent to compilers or programmers Learn from the mistakes of ITANIUM ! Remember the success of OOO execution Oct 31st 2007 * 9 Reliability Issues --Niti Shrinking transistor sizes lower voltages Increased transient faults, process variations – leakage power and frequency variations, hard errors, interconnect noise Many-core – “Many cores” may not work reliably Some cores will end up providing redundancy Heterogeneous cores may be able to help Simple in-order cores can provide redundancy at low cost The compute power gain of many-core can get offset by reliability requirements of the system Oct 31st 2007 * On-Chip Sensor Networks  --Nathaniel, Amlan Analog sensors everywhere! Need to monitor power, voltage droop, variation, critical paths, delays, slew ra