uart verilog源代码.docVIP

`timescale 1ns / 100ps module uart (dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn,din,tbre,tsre,wrn,sdo); output tbre ;output tsre ;output sdo ;input [7:0] din ;input rst ;input clk16x ;input wrn ;input rxd ;input rdn ;output [7:0] dout ;output data_ready ;output framing_error ;output parity_error ; rcvr u1 (dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn) ; txmit u2 (din,tbre,tsre,rst,clk16x,wrn,sdo) ; endmodule******************************************************************************************** `timescale 1 ns / 1 ns module rcvr (dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn) ; input rxd ;input clk16x ;input rst ;input rdn ;output [7:0] dout ;output data_ready ;output framing_error ;output parity_error ; reg rxd1 ;reg rxd2 ;reg clk1x_enable ;reg [3:0] clkdiv ;reg [7:0] rsr ;reg [7:0] rbr ;reg [3:0] no_bits_rcvd ; reg data_ready ; reg parity ;reg parity_error ;reg framing_error ; wire clk1x ; assign dout = !rdn ? rbr : 8bz ; always @(posedge clk16x or posedge rst)beginif (rst)beginrxd1 = 1b1 ;rxd2 = 1b1 ;endelsebeginrxd1 = rxd ;rxd2 = rxd1 ;endend always @(posedge clk16x or posedge rst)beginif (rst)clk1x_enable = 1b0;else if (!rxd1 rxd2)clk1x_enable = 1b1 ;else if (no_bits_rcvd == 4b1100)clk1x_enable = 1b0 ;end always @(posedge clk16x or posedge rst or negedge rdn)beginif (rst)data_ready = 1b0 ;else if (!rdn)data_ready = 1b0 ;elseif (no_bits_rcvd == 4b1011)data_ready = 1b1 ;end always @(posedge clk16x or posedge rst)beginif (rst)clkdiv = 4b0000 ;else if (clk1x_enable)clkdiv = clkdiv +1 ;end assign clk1x = clkdiv[3] ; always @(posedge clk1x or posedge rst)if (rst)beginrsr = 8b0 ;rbr = 8b0 ;parity = 1b1 ;framing_error = 1b0 ;parity_error = 1b0 ;endelsebeginif (no_bits_rcvd = 4b0001 no_bits_rcvd = 4b1001)beginrsr[0] = rxd2 ;rsr[7:1] = rsr[6:0] ;parity = parity ^ rsr[7] ;endelse if (no_bits_rcvd == 4b1010)beginrbr = rsr ;endelse if