7-1 RS锁存器.pptVIP

Chapter 7 Sequential Logic Design Principles 时序逻辑设计原理 (P521) Chapter 7 Sequential Logic Design Principles第７章　　时序逻辑设计原理 7.1 Bistable Elements 双稳态元件 7.2 latches and Flip-Flops 锁存器与触发器 7.3 Clocked Synchronous State- Machine Analysis 同步时钟状态机的分析 7.4 Clocked Synchronous State- Machine Design 同步时钟状态机的设计 Review of Basic Concept (基本概念回顾) Logic circuits are classified into two types（逻辑电路分为两大类） combinational logic circuit（组合逻辑电路） A combinational logic circuit is one whose outputs depend only on its current inputs.（任何时刻的输出仅取决与当时的输入） characteristic：no feedback circuit sequential logic circuit（时序逻辑电路） The outputs of a sequential logic circuit depend not only on the current inputs, but also on the past sequence of inputs, possibly arbitrarily far back in time.（任一时刻的输出不仅取决于当时的输入，还取决于过去的输入顺序） Basic Concepts (基本概念) Logic Circuits are Classified into Two Types (逻辑电路分为两大类)： Combinational Logic Circuit （组合逻辑电路） Sequential Logic Circuit （时序逻辑电路） Basic Concepts (基本概念)(P521) Combinational Logic Circuit （组合逻辑电路） Basic Concepts (基本概念)(P521) Sequential Logic Circuit （时序逻辑电路） Basic Concepts (基本概念)(P522) Sequential Logic Circuit （时序逻辑电路） Basic Concepts (基本概念)(P522) Sequential Logic Circuit （时序逻辑电路） Basic Concepts (基本概念)(P522) Sequential Logic Circuit （时序逻辑电路） Why need we the sequential circuit? 7.1 Bistable Elements  双稳态元件 7.1.3 Metastable Behavior  亚稳态特性(P525) 7.2 Latches and Flip-Flops 锁存器与触发器(P526) —— Latches and flip-flops are the basic building blocks of most sequential circuits. 是大多数时序电路的基本构件 Latch（锁存器） 根据输入，直接改变其输出（无使能端） 有使能端时，在时钟信号的有效电平之内都可根据数据直接改变其输出状态 Flip-Flop，F/F（触发器） 只在时钟信号的有效边沿改变其输出状态. 7.2 Latches and Flip-Flops(锁存器与触发器) S-R Latch (S-R锁存器) S-R Latch with Enable (具有使能端的S-R锁存器) D Latch (D锁存器) Edge-Triggered D Flip-Flops (边沿触发式D触发器) Edge-Triggered D Flip-Flops with Enable (具有使能端的边沿触发式D触发器) 7