操作系统_内存管理教案详解.pptVIP

作业 什么是内部碎片；什么是外部碎片 画出最基本的分页地址变换机构。 分页和分段的主要区别是什么？ 页表存放在内存中 访问一个逻辑地址中的内容需要两次访问内存 第一次：页表项，进而转换成物理地址 第二次：对应物理地址中的内容 速度：CPU vs. 2倍访存 解决方案：高速缓存（块表，TLB）Translation Lookaside Buffer 基本的地址变换机构 Page table is kept in main memory, Table Base Register (PTBR) Points to the page table currently used table length register (PRLR) Indicates size of the page table Context switch + 3 b Effective memory-access time, time needed for every data/instruction access 需要2次访存 Access the page table Access the data/instruction Solution: A special fast-lookup hardware cache called associative registers or translation look-aside buffers (TLBs) 联想存储器，快表 Associative registers Each register : a key a value Parallel search (high speed) Expensive, typically 8~2048 entries Address translation (A′, A′′) If A′ is in associative register, get frame # out. Otherwise get frame # from page table in memory 联想存储器，快表 TLB miss（TLB缺失） If the page number is not in the associative registers Get store Hit ratio（命中率） The percentage of times that a page number is found in the associative registers Context switch ? TLB flushed TLB replacement algorithm 具有块表的地址变换机构 + Effective Access Time 有效存取时间 设： Associative Lookup = ? time unit;memory cycle time = t time unit;Hit ratio = ? Effective Access Time (EAT) EAT = (t + ?) ? + (2t + ?)(1 – ?) = 2t + ? – t? If ?(20 ns), t(100 ns), ?1(80%), ?2(98%): TLB hit: 20+100=120 ns TLB miss: 20+100+100=220 ns EAT1 = 120*0.8 + 220 * 0.2 = 140 ns EAT2 = 120*0.98 + 220 * 0.02 = 122 ns 思考 从页表中读取数据的时间开销是5ns，从块表中读取数据的开销则是1ns，为使平均开销降为1ns，则块表的命中率至少为多少？ Memory Protection 内存保护 If page size 2n, page frame is aligned at 2n, so … Memory protection implemented by associating protection bit with each frame Provide read only, read-write, execute-only protection or… Valid-invalid “valid”: the associated page is in the process’ logical address space, and is thus a legal page. “invalid”: the page is not in the process’ logical address space. Valid/invalid bit example Address