中科院_专用集成电路设计_作业5实用技术.docxVIP

Assignment 5 Analyze SE of Actel ACT (Figure 5.4(d)) with any possible combinations of C1, C2 and CLR C controls. a. Which functions does SE support? b. Verify these functions by using Modelsim simulator at logic level or HSPICE circuit simulator. Figure 5.4(d) Actel ACT 2 and ACT 3 Logic Modules: The equivalent circuit (without buffering) of the SE (sequential element) Solution: a）由图中逻辑关系可以得出 Q=(C1·/C2+CLR)·(/(C1⊙C2) ·(/S1·D+F1·S1) ·MC·F1+(C1⊙C2)·Q)·(CLR+C1·/C2) b)由于在设计中C1和C2至少要有一个接CLK(否则设计无意义)则编写相应的Hspice仿真代码如下 * homeworkfive.sp--- ACTEL ACT . D:\Program Files (x86)\synopsys\Hspice_D-2010.03-SP1\MM018.L TT * Set TSMC 0.18um library .option list node post .tran 50p 5000p * Starts a transient analysis that simulates a circuit at a specific time. * format: .TRAN tstep1 tstop1 START=val UIC .probe tran + clock=par(v(C1)) + data=par(v(d)) + q=par(v(q)) * Use this command to save output variables to interface and graph data * files. The parameter can be a node voltage or a reasonable expression. .ic v(q)=0 $ set initial value. * The node voltages that you specify in the .IC statement are fixed to * determine the DC operating point. They are used only in the first * iteration to set an initial guess for the DC operating point analysis. * waveforms vdata d gnd pwl(0 0 100p 0 140p 1.8p 800p 1.8 840p 0 3.3n 0 3.34n 1.8) * pulse( v1 v2 td tr tf pw per ) vclk c1 gnd pulse(0,1.8 300p,40p,40p 800p,1600p) vclr clr gnd pwl(0 1.8 4.2n 1.8 4.24n 0) vc1 c2 gnd 0 * * top: d-latch * xclkinv clck clckn inv $ enable if asymmetric (overlapping) positive * and negative clocks are used xact d c1 c2 clr q act cw1 qm gnd .1f $ add wire delay cw2 q gnd .1f * * macro definitions * ********************************** * * n-channel mosfet * * drain gate source .subckt nmos n1 n2 n3 mn n1 n2 n3 gnd NCH l=0.2u w=0.4u ad=0.2p^2 pd=0.4u as=0.2p^2 ps=0.4u .ends nmos * * p-channel mosfet * * drain gate source .subckt pmos n1 n2 n3 v