FPGA常见警告.docVIP

1.Found clock-sensitive change during active clock edge at time time on register name原因：vector source file中时钟敏感信号（如：数据，允许端，清零，同步加载等）在时钟的边缘同时变化。而时钟敏感信号是不能在时钟边沿变化的。其后果为导致结果不正确。措施：编辑vector source file 2.Verilog HDL assignment warning at location: truncated value with size number to match size of target (number原因:在HDL设计中对目标的位数进行了设定,如:reg[4:0] a;而默认为32位,将位数裁定到合适的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数 3.All reachable assignments to data_out(10) assign 0, register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了 4.Following 9 pins have nothing, GND, or VCC driving datain port -- changes to