邓仰东：基于GPU的高性能嵌入式计算_IT168CUDA技术沙龙分解.pptVIP

High Performance Embedded Computing with Massively Parallel Processors;Outline;High Performance Embedded Computing;~$1M;Implications of the Prohibitive Cost;Multicore Machines Are Really Powerful!;Implications;Outline;Background and motivation GPU based routing processing Routing table lookup Packet classification Deep packet inspection GPU microarchitecture enhancement CPU and GPU integration QoS-aware scheduling;Ever-Increasing Internet Traffic;Fast Changing Network Protocols/Services;;Internet Router;Current Router Solutions;Outline;Critical Path of Routing Processing;GPU Based Software Router;Routing Table Lookup;Routing Table Lookup;GPU Based Routing Table Lookup;Packet Classification;Packet Classification;GPU Based Packet Classification;GPU Based Packet Classification;Deep Packet Inspection (DPI);GPU Based Deep Packet Inspection (DPI);GPU Based Deep Packet Inspection (DPI);Outline;Limitation of GPU-Based Packet Processing;Microarchitectural Enhancements;Microarchitectural Enhancements;Results: Throughput ;Results: Packet Latency;Outline;High Performance Radar DSP Processor;Research Objectives;Current DSP Platforms;High Performance Radar DSP Processor;HPEC Challenge - Radar Benchmarks;GPU Implementation;Performance Results;Performance Comparison;Instruction Profiling;Thread Profiling;Off-Chip Memory Profiling;Limitation;High Performance Radar DSP Processor;Key Idea - Hardware Architecture;Key Idea – Parallel Code Generation;Key Idea – Internal Representation as KPN;Scheduling and Optimization on KPN;Key Idea - Low Power Techniques;Outline;Conclusion