LowPowerDesignofCMOSCircuitsCMOS电路的低功耗设计.ppt

Power-Delay Tradeoff Nov 19, 2009 * Agrawal: Low Power Design Leakage Dynamic Power Optimization 70nm CMOS c7552 Benchmark Circuit @ 90oC Leakage exceeds dynamic power Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff,” Journal of Low Power Electronics (JOLPE), vol. 2, no. 3, pp. 378-387, December 2006. Nov 19, 2009 * Agrawal: Low Power Design Power Constrained Test Scheduling R1 R2 M1 M2 R3 R4 A datapath Nov 19, 2009 * Agrawal: Low Power Design Minimum Test Time LFSR1 LFSR2 M1 M2 MISR1 MISR2 Test time Test power T1: test for M1 T2: test for M2 Nov 19, 2009 * Agrawal: Low Power Design Minimum Test Power R1 LFSR2 M1 M2 MISR1 MISR2 Test time Test power T1: test for M1 T2: test for M2 Nov 19, 2009 * Agrawal: Low Power Design Testing of MCM and SOC Test resources: Typically registers and multiplexers that can be reconfigured as test pattern generators (e.g., LFSR) or as output response analyzers (e.g., MISR). Test resources (R1, . . .) and tests (T1, . . .) are identified for the system to be tested. Each test is characterized for test time, power dissipation and resources it requires. Nov 19, 2009 * Agrawal: Low Power Design Resource Allocation Graph(A Bipartite Graph) T1 T2 T3 T4 T5 T6 R2 R1 R3 R4 R5 R6 R7 R8 R9 Nov 19, 2009 * Agrawal: Low Power Design Test Compatibility Graph (TCG) T1 (2, 100) T2 (1,10) T3 (1, 10) T4 (1, 5) T5 (2, 10) T6 (1, 100) Tests that form a clique can be performed concurrently. Power Test time Pmax = 4 Nov 19, 2009 * Agrawal: Low Power Design Find All Cliques in TCG CLIQUE NO. i TEST NODES TEST LENGTH, Li POWER, Pi 1 T1, T3, T5 100 5 2 T1, T3, T4 100 4 3 T1, T6 100 3 4 T1, T5 100 4 5 T1, T4 100 3 6 T1. T3 100 3 7 T2, T6 100 2 8 T2, T5 10 3 9 T3, T5 10 3 10 T3, T4 10 2 11 T1 100 2 12 T2 10 1 13 T3 10 1 14 T4 5 1 15 T5 10 2 16 T6 100 1 Nov 19, 2009 * Agrawal: Low Power Design Integer Linear Program (ILP) For each clique (test session) i, define: Integer variable, xi = 1, test session selected, o