0914问题.pptVIP

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 电子与通信工程系 * library ieee; use ieee.std_logic_1164.all; entity comp_good is port(a: in std_logic; b: in std_logic; q: out std_logic); end comp_good; architecture one of comp_good is begin process(a,b) begin if ab then q=1; else q=0; end if; end process; end one; 电子与通信工程系 * library ieee; use ieee.std_logic_1164.all; entity comp_bad is port(a: in std_logic; b: in std_logic; q: out std_logic)