RISC_CPU源代码.docVIP

module clk_gen (clk,reset,clk1,clk2,clk4,fetch,alu_clk); input clk,reset; output clk1,clk2,clk4,fetch,alu_clk; wire clk,reset; reg clk2,clk4,fetch,alu_clk; reg[7:0] state; parameter S1 = 8 S2 = 8 S3 = 8 S4 = 8 S5 = 8 S6 = 8 S7 = 8 S8 = 8 idle = 8 assign clk1 = ~clk; always @(negedge clk) if(reset) begin clk2 = 0; clk4 = 1;