4位二进制加减可控计数器.docVIP

4位二进制加减可控计数器： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT CLK,RST,EN,MODE : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR 3 DOWNTO 0 ; COUT : OUT STD_LOGIC ; END CNT10; ARCHITECTURE behav OF CNT10 IS BEGIN PROCESS CLK, RST, EN VARIABLE CQI : STD_LOGIC_VECTOR 3 DOWNTO 0 ; BEGIN IF RST 1 THEN CQI : OTHERS 0 ; ELSIF CLKEVENT AND CLK 1 THEN IF EN 1 THEN IF MODE 1 THEN IF CQI 0 THEN CQI : 1111; ELSE CQI : CQI-1; END IF; ELSIF CQI 15 THEN CQI : CQI + 1; ELSE CQI : OTHERS 0 ; END IF; END IF; END IF; IF CQI 15 THEN COUT 1; ELSE COUT 0; END IF; CQ CQI; END PROCESS; END behav;