汉字点阵显示VHDL源程序.docVIP

汉字点阵显示VHDL源程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity hzxs is port(clk1,clk2:in std_logic; rd:out std_logic; we: out std_logic; ledw:out std_logic_vector(2 downto 0); d:out std_logic_vector(0 downto 7)); end hzxs; architecture hav of hzxs is signal count:std_logic_vector(0 to 2); signal a: std_logic_vector(3 downto 0); begin process(clk2) begin if clk2event and clk2=1 then count=count+1; end if; ledw=count; a(2 downto 0)=count; end process; process(clk1) begin if clk1event and clk1=1 then a(3)=not a(3); end if; end process; process(a) begin case a is when0000=d--数 when0001=d when0010=d when0011=d when0100=d when0101=d when0110=d when0111=d when1000=d--字 when1001=d when1010=d when1011=d when1100=d when1101=d when1110=d when1111=d when others=d end case; end process; rd=1; we=0; end hav; 数字抢答器VHDL源程序 1）抢答器QDQ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity qdq is port(clr:in std_logic; a,b,c,d:in std_logic; an,bn,cn,dn:out std_logic); end qdq; architecture hav of qdq is signal ss:std_logic_vector(0 to 3); begin ss=abcd; process(clr,a,b,c,d) begin if clr=1 then case ss is when 1000=an=1;bn=0;cn=0;dn=0; when 0100=an=0;bn=1;cn=0;dn=0; when 0010=an=0;bn=0;cn=1;dn=0; when 0001=an=0;bn=0;cn=0;dn=1; when others=an=0;bn=0;cn=0;dn=0; end case; elsif clr=0 then an=0; bn=0; cn=0; dn=0; end if; end process; end hav; 2）计分器JFQ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity jfq is port(en1:in std_logic; clk3:in std_logic; bs:out std_logic_vector(3 downto 0); ss:out std_logic_vector(3 downto 0); gs:out std_logic_vector(3 downto 0); add:in s