AddressTranslationwithPaging.pptVIP

Address Translation with Paging Case studies for X86, SPARC, and PowerPC Overview Page tables What are they? (review) What does a page table entry (PTE) contain? How are page tables organized? Making page table access fast Caching entries Translation lookaside buffer (TLB) TLB management Generic Page Table Memory divided into pages Page table is a collection of PTEs that maps a virtual page number to a PTE Organization and content vary with architecture If no virtual to physical mapping = page fault Generic PTE PTE maps virtual page to physical page Includes some page properties Valid?, writable?, dirty?, cacheable? Real Page Tables Design requirements Minimize memory use (PT are pure overhead) Fast (logically accessed on every memory ref) Requirements lead to Compact data structures O(1) access (e.g. indexed lookup, hashtable) Examples: X86 and PowerPC X86-32 Address Translation Page tables organized as a two-level tree Efficient because address space is sparse Each level of the tree indexed using a piece of the virtual page number for fast lookups One set of page tables per process Current set of page tables pointed to by CR3 CPU walks the page tables to find translations Accessed and dirty bits updated by CPU 4K or 4M (sometimes 2M) pages X86-32 PDE and PTE Details X86-32 Page Table Lookup Top 10 address bits index page directory and return a page directory entry that points to a page table Middle 10 bits index the page table that points to a physical memory page Bottom 12 bits are an offset to a single byte in the physical page Checks made at each step to ensure desired page is available in memory and that the process making the request has sufficient rights to access the page X86-32 and PAE Intel added support for up to 64GB of physical memory in the Pentium Pro - called Physical Address Extensions (PAE) Introduced a new CPU mode and another layer in the page tables In PAE mode, 32-bit VAs map to 36-bit PAs Single-process address space is still 32 bits