DLT_Overview.pptVIP

* 1 CCM / 1 bCEM per Rack * * * * * * * * * * RLC : segmentation MAC : multiplexage PDU(N+1) = SDU (N) * * * * * * * * * * * * * * DLT / bCEM RLC/MAC DL scheduler C Plane messages Documents Code browsing DLT / bCEM RLC/MAC DL scheduler C Plane messages Documents Code browsing RAC enodeB bCEM board P4080 core 1 core 2 core 3 core 4 core 5 core 6 core 7 core 8 DSP A core 1 core 2 core 3 DSP B core 1 core 2 core 3 DSP C FPGA A comb FPGA BC Layer1 zBRC Layer2 core 1 core 2 core 3 core 1 core 2 core 3 core 1 core 2 core 3 core 1 core 2 core 3 P4080 core 7 core 6 core 5 core 1 core 3 core 2 core 4 core 0 ULT Cell 0 Cell 1 Cell 2 HRAL BRC Cell 0 debug Cell 1 Cell 2 Ce proxy DLT ULT DLT ULT DLT L2CfgTx ULU ULU ULU process thread 3 processes : 1 process for each cell L2CfgRx L2CfgTx L2CfgRx L2CfgTx L2CfgRx ULU optionnal ULU optionnal ULU optionnal ULU optionnal ULU optionnal ULU optionnal L2SW process cell x DLT DLS MAC DL RLC DL Sysinfo RACH 3-4 Paging HARQ Supervision ULT MAC CE crc hand RACH 1-2 L1 meas UL SCD PHICH DCI conc Pwr Ctrl Spv RT core x+1 ULU RLC MAC UL Spv RT core 6 optionnal core x, x+1 L2CfgTx L2CfgRx SPV ULT NRT SPV DLT NRT core 6 BRC HRAL uplink RLC SDU (ethernet) downlink RLC SDU (ethernet) PUSCH UCI PBCH, PDSCH PDCCH, PHICH PCFICH, sched info, RACH req RACH Msg2 MAC CE CRC, SINR PWR RACH Msg1 DCI PDSCH ctrl SRIO DLT ULT FPGA _ A FPGA _ BC DSP CCM ( Callp ) Ring buffer PBCH / PDSCH Ring buffer : FAC ( PDCCH and PHICH , PCFICH … ) DL Grant Ethernet : DL PDCP or RRC msg SRIO : ACKNACK / CQI / PMI / RI DL Traffic ULU STATUS PDU P bit L 1 Tx thread Ring buffer : DSP z-Scheduling information SRIO : PBCH / PDSCH SRIO : FCC SRIO : SRIO : TA P 4080 Platform Ring buffer : UCI / PUCCH Ring buffer : TA PDCP receiver Ring buffer : DL RLC SDU z-Scheduling information DLT / bCEM RLC/MAC DL scheduler C Plane messages (from BRC) Documents Code browsing 3GPP