PLC邏辑控制系统循环时间的设计.docVIP

PLC逻辑控制系统循环扫描时间的设计 邱公伟　巫淑萍 摘　要　给出了设计PLC逻辑控制系统循环扫描时间的4个限制条件。满足这些条件可保证逻辑等价性，防止信号丢失，从而避免表面正确的梯形图内含的危险及隐患，减少I／O响应时间，提高控制精度，保证计时器的正常工作。关键词：循环扫描时间　逻辑等价性　I／O响应时间　时基限制条件 The Design of the Cycling Scanning Time for PLC Logical Control System Abstract　Four limits in Design of the cycling scanning time of PLC logic control system are given． Based on these conditions the logic equivalence can be ensured and the signal will not be lost． Thus the inherent dangerous and hidden peril may be removed from the correct looking ladder logic， the I／O response will be faster， the control accuracy will be enhanced a