大学毕业论文_基于fpga的irigb码基带产生电路的设计与实现.docVIP

基于FPGA的IRIG-B码基带产生电路的设计与实现 中文摘要 本论文的主要目的是设计用于将接收到的时间信息进行IRIG-B编码的电路，实现基于直接序列扩频通信原理以及调制的基带信号的数字信号处理。编码电路主要由时间接收单元、预处理单元和IRIG-B编码器构成。发送电路主要由基带处理单元和频带处理单元构成。用Verilog HDL语言完成整个所有模块的设计，然后连接所有电路模块，最后通过SignalTap II Logical Analysis tool进行功能仿真。所有工作在Altera公司的Cyclone ?Ⅲ E系列FPGA（现场可编程门阵列）芯片中实现。 论文首先提出了一种适用于时间接收与发送的基于FPGA的IRIG-B码基带产生电路。然后讨论了整个电路中各模块的理论依据以及详细的实现方法。其中编码部分主要包括GPS接收模块、时间预处理模块、IRIG-B编码器，发送部分主要模块包括差分编码器、直接序列扩频模块和BPSK调制模块。最后编译工程并下载到DE0开发板Altera 公司上进行仿真验证，并给出了模块仿真结果。仿真结果工作，整性能稳定，占用相对较少资源，设计要求。 关键词：GPS；FPGA；IRIG-B码；扩频通信 Design and Implementation of IRIG-B Code basebandCircuit based on FPGA Abstract The main purpose of this paper is?to?design?IRIG-B?code circuit for the received time information, then implement the direct sequence spread spectrum?and the?DBPSK signal modulation?based on digital signal processing.?Coding?circuit is mainly constituted?by the?time?receiving unit,?processing?unit and IRIG-B?encoder.?And the transmitting circuit?is mainly composed of?baseband?processing unit and the?band processing?unit.?All modules of the whole project are completed with Verilog HDL language,?and then?connect all?modules of the system,?and finally got functional simulation through the SignalTap?tool.?All the work is completed on?Altera,?Cyclone?III E series FPGA?(field programmable gate array)?chip. Firstly the paper proposes an IRIG-B Code baseband circuit applied to time receiving, processing and sending based on FPGA. And then discusses the theoretical basis of?each?module?circuit?as well as the?detailed realization method.?The coding?part mainly includes?GPS module,?time?pre-processing module and?IRIG-B encoder,?and the sending?part includes differential encoder,?direct sequence spread spectrum?module and?BPSK module.?All the modules?are given the simulation waveforms,?and finally compiled and downloaded to the?Alteras DE0 development board?for simulation.