EDA技术实用教程(第二版)潘松黄继业第2版第9章_VHDL基本语句课件教学.pptVIP

【例9-35】 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; USE ieee.std_logic_arith.ALL; ENTITY crcm IS PORT (clk, hrecv，datald : IN std_logic; sdata : IN std_logic_vector(11 DOWNTO 0); datacrco : OUT std_logic_vector(16 DOWNTO 0); datacrci : IN std_logic_vector(16 DOWNTO 0); rdata : OUT std_logic_vector(11 DOWNTO 0); datafini : OUT std_logic; ERROR0, hsend : OUT std_logic); END crcm; ARCHITECTURE comm OF crcm IS CONSTANT multi_coef : std_logic_vector(5 DOWNTO 0) := 110101; --