ppt课件-f p g a power reduction using configurable dual- vdd（f p g使用可配置的双核vdd功率降低）.pptVIP

Minimal Skew Clock Embedding Considering Time-Variant Temperature Gradient Hao Yu, Yu Hu, Chun-Chen Liu and Lei He EE Department, UCLA Presented by Yu Hu Partially supported by NSF and UC MICRO funds. Outline Backgrounds and Motivations Modeling and Problem Formulation Algorithms Experimental Results Conclusions Clock Tree Synthesis in Synchronous Circuits Clock signals synchronize data transfer between functional elements in synchronous design Different clock structures exist [Tree, Mesh, Hybrid, etc] Clock skew is the delay difference between two sinks of clock tree Clock skew b