西电verilog课件第六章.ppt

* * Microelectronics School Xidian University * * Microelectronics School Xidian University module fastaddder_4 (sum,c_out,a,b,c_in); input [3:0] a,b; //the other of add number input c_in; //carry in from before level output [3:0] sum; //the add of two input output c_out; //carry out to next level wire [4:0] g,p,c; //wire between every c_out and c_in assign c[0]=c_in; assign p=a^b; assign g=ab; assign c[1]=g[0]|(p[0]c[0]); assign c[2]=g[1]|(p[1](g[0]|(p[0]c[0]))); assign c[3]=g[2]|(p[2](g[1]|(p[1](g[0]|(p[0]c[0]))))); assign c[4]=g[