EDA实验编程答案.docVIP

实验三、数字频率计 4位数字频率计控制模块 module fre_pm1(clk,rst,count_en,count_clr,load); input clk,rst;output count_en,count_clr,load;reg count_en,load; always @(posedge clk) begin if(rst) begin count_en=0;load=1;end else begin count_en=~count_en; load=~count_en; end end assign count_clr=~clkload; endmodule 四位频率计计数子模块 module a1(out,cout,en,clr,clk); input en,clr,clk;output[3:0] out;output cout;reg[3:0] out; always @(posedge clk or posedge clr) begin if(clr) out=0; else if(en) begin if(out==9) out=0;else out=out+1;end end assign cout=((out==9)en)?1:0; endmodule 十六位锁存器模块 module b1(qo,