5.支持系统Part3——F28x–GPIO+PLL+WD+LPM讲述.ppt

Lab 3B Add start/stop control: use Lab 2 to start: GPIO-D1 and D6 are connected to two push-buttons. If they are pushed, the input level reads 0, if released 1. Use D1 to start the LED “Knight-rider” and D6 to halt it. If D1 is pushed again the sequence should continue again. To do so, you also need to add the instructions to initialise GPIO-D * 1 * * NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire operating range. The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below: ? Fundamental mode, parallel resonant ? CL (load capacitance) = 12 pF ? CL1 = CL2 = 24 pF ? Cshunt = 6 pF ? ESR range = 25 to 40 Ω F240的wotchdog 系统复位后，无论VCCP引脚接地还是5V，WD总是被使能，且对最快的输入信号WDCLK（假如为16384Hz，EVM板上为15625Hz）计数，约15.625mS后将会产生溢出，并复位系统。 SYSSR的HP0位为1时（即VCCP引脚接5V），可以通过程序禁止WD WDDIS=0 使能WD KICK_DOG WDDIS=1 禁止WD 当HP0为0（即VCCP引脚接地）时，WD始终有效，不受WDDIS位控制。KICK_DOG. 时间： 15.625mS～1S * * * * * * 3 - * 32-Bit-Digital Signal Controller TMS320F2812 Texas Instruments Incorporated European Customer Training Center University of Applied Sciences Zwickau (FH) Module 3: F28x –Digital I/O C281x Block Diagram 32x32 bit Multiplier Sectored Flash A(18-0) D(15-0) Program Bus Data Bus RAM Boot ROM 22 32-bit Auxiliary Registers 3 32 bit Timers Realtime JTAG CPU Register Bus R-M-W Atomic ALU PIE Interrupt Manager 32 32 32 Event Manager A Event Manager B 12-bit ADC Watchdog McBSP CAN2.0B SCI-A SCI-B SPI GPIO C28x GPIO Functional Block Diagram ? ? ? 1 0 MUX Control Bit 0 = I/O Function 1 = Primary Function Primary Peripheral Function I/O DAT Bit (R/W) In Out ? I/O DIR Bit 0 = Input 1 = Output GPxMUX GPxDIR GPxDAT GPxSET GPxCLEAR GPxTOGGLE QUALPRD reserved 7