电子科技大学“数字逻辑设计及应用”数字逻辑6-2.pptVIP

* * Register and Synchronous design Chapter 6 Sequential control design principles D latch To avoid the inputs SR=11 and 00, S and R is made complement ! When C=1, Q=D; when C=0, state hold ! The state is decided by the input Directly ! when C=1 , the metastable will never happen ! Sequential analyze for D latch Read and write control for D latch D flip-flop CLK=0, master enable, slave hold ; input come in ;CLK=1, master hold, slave enable ; input cut off. The state changed only at the trigger time ! Sequential analyze for DFF Sequential analyze for DFF Characteristic equation of DFF Stat