电子科技大学“数字逻辑设计及应用”数字逻辑7-3.pptVIP

* * FSM design: Sequence detector Chapter 7 Finite state machine design Sequence detector design Output 1 only when input sequence be 1011 How to set the states? Sequence detector design s0 initial state s1 get 1 bit 1; s2 get 2 bits 10; s3 get 3 bits 101; s4 get 4 bits 1011, output 1 Set n+1 states to detect an n-bits sequence Transition of the state Sequence detector design Some guidelines for state assignment The code for initial state should be easily reset; The code for neighboring state should be neighboring , frequently used states should be first considered. Sequen