电子科技大学“数字逻辑设计及应用”数字逻辑X-2.pptVIP

* * Text entry with Verilog HDL Chapter 5 Design simulation and HDL Verilog HDL structure Use text entry to replace schematic entry: Large design and time delay can be easily described ; Modification can be easily done. Verilog HDL structure Hardware module： Name、port 、 structure 、function Module name and IO module majority (a,b,c,f); input a,b,c; output f; … … endmodule Signal :port and wire Two kinds of signal : port : input and output; wire : any connect nets in module; The value of signals: 0 1 z x module majority (a,b,c,f); input a,b,c; output f; wire w1,w2,w3;