电子科技大学“数字逻辑设计及应用”数字逻辑X-3.pptVIP

* * Time simulation Chapter 5 Design simulation and HDL Describe for time delay Define the time dimension and time precision timescale 100 ns/1 ps Describe the time delay for device assign #19 w1=~(ab); assign #41 f=~(w1|w2|w3); module majority (a,b,c,f); input a,b,c; output f; wire w1,w2,w3; assign #19 w1=~(ab); assign #19 w2=~(bc); assign #19 w3=~(ac); assign #40 f=~(w1w2w3); endmodule Describe for time delay assign #3 a1=a;assign #3 a2=a; assign #3 b1=b;assign #3 b2=b; assign #3 c1=c;assign #3 c2=c; assign #19 w1=~(a1b1); assign #19 w2=~(b2c1); assign #19 w3=~(a2c2); assig