shiftinstructions.docVIP

SHIFT INSTRUCTIONS LOGICAL SHIFT INSTRUCTIONS ARITHMETIC SHIFT INSTRUCTIONS (for unsigned operands) (for signed operands) SHL (Shift Left) SAL (Shift Arithmetic Left) SHR (Shift Right) SAR (Shift Arithmetic Right) Syntax: SXX Destination , Count where: Destination is either a register or memory operand. Count is either 1 or the CL register for the 8086 Processor. (If the destination is to be shifted more than once, the number of shifts is put in CL) Count is an immediate 8-bit value or the CL register for 80186 and higher Intel Processors. The value in CL does not change when a shift instruction is executed. A shift count is a modulo-32 count. Hence, a shift count of 32 or more will shift data count % 32 times. Shift instructions affect CF, OF, PF, SF, and ZF. The AF flag is undefined. SHL is equivalent to SAL The 80386 and higher Intel processors also have double-precision shift instructions: SHLD Destination, Source, count SHRD Destination, Source, count Both instructions function with two 16- or 32-bit registers, or with one 16-bit or 32-bit memory operand with a register of the same size. SHL (SHIFT LEFT) SHL shifts the msb into the Carry Flag; the current value of the Carry Flag is lost. Each of the remaining bits is shifted left and 0 is shifted into the lsb. CF . . . 0 If the count operand is greater than 1, OF is undefined. If the count is 1, OF is cleared when the highest bit of the destination and the CF have the same value after the shift; otherwise it is set. Example: MOV CL , 3 SHL BL , CL Effect: CF BL b5 b4 b3 b2 b1 b0 0 0 0 Shifting left a Destination operand n times multiplies it by 2n Multiplication by a non-multiple of 2 can be achieved by a combination of SHL, MOV, ADD, or SUB instructions. Such multiplications are usually more efficient than multiplications using the MUL (Multiplication) instruction. Example: Multiply