基于FPGA的时间数字转换器设计稿学士学位专业论文.docxVIP

NANCHANG UNIVERSITY 学 士 学 位 论 文 THESIS OF BACHELOR （2009—2013年） 题 目 基于FPGA的时间-数字转换器设计 学 院： 信息工程学院 系 电子系 专业班级： 电子信息工程093班 基于FPGA的时间-数字转换器设计 摘要 时间是物质存在和运动的基本属性之一，它是科学研究、科学实验和工程技术等领域的必不可少的参量。时间-数字转换器作为时间测量技术的核心，在诸多领域都有广泛的应用。实现时间-数字转换电路的方法有许多种，如计数器法、电流积分法、门延迟法以及FPGA法等。本论文设计的是基于FPGA的时间-数字转换器，设计思想是以计数器为粗时间间隔测量单元，门延迟为细时间间隔测量单元，最终基于FPGA实现TDC系统。设计借助了Verilog HDL语言对FPGA进行设计，完成了边缘检测、计数器及串口输出的软件设计，实现了测量范围为30min，分辨率达1ns的大范围、高分辨率TDC系统的设计。本系统可移植性强，在提高时钟频率和门延迟精度后可应用于微粒子探测、激光测距和定时定位等领域。 关键词： 时间-数字转换器 FPGA 计数器 门延迟 分辨率 Design of Time to Digital Converter based on FPGA Abstract Time is one of the basic attribute of material’s existence and exercise, it’s an essential parameter of scientific researches, scientific experiments, engineering technology and other technology fields. Time-digital converter, as a time measurement technology core, are widely used in many fields. There are many ways to implement the time-digital converter, such as the counter method, the current integration method, the gate delay method and the FPGA method. This thesis designed a FPGA based TDC, the design idea is using the counter as a crude time interval measurement, the gate delay as a precise time interval measurement, and finally, the system is achieved by the FPGA. In the design, with the language of Verilog HDL, we achieved the software design of the edge detection, the counter and the outputting of serial. A measurement range of 30min, 1ns resolution of the large-scale, high-resolution TDC system is designed. This system is portable, if the clock frequency and the accuracy of gate delay are improved, it can be used in particle detection, laser ranging and timing positioning and any other fields. Keywords: Time to Digital Converter; FPGA; Counter; Gate delay; Resolution 目录 摘要.................................................................................................................................I ABSTRACT.....................