chapitre1.ppt

Harbin Institute of Technology, China Prof. Y. HU * July，2014 Stability of Amplifiers Phase margin: F(w) resistive circuits → Harbin Institute of Technology, China Prof. Y. HU * July，2014 Stability of Amplifiers (cont.) One-Pole System: Phase margin fM > 0 System stable Harbin Institute of Technology, China Prof. Y. HU * July，2014 Stability of Amplifiers (cont.) Three-pole system: Phase margin fM < 0 System instable - 20 dB/dec - 40 dB/dec - 60 dB/dec Harbin Institute of Technology, China Prof. Y. HU * July，2014 Stability of Amplifiers (cont.) Compensation of Frequency: introduce a principal pole to have a positive phase margin Method is simple. Reduce the bandwidth Harbin Institute of Technology, China Prof. Y. HU * July，2014 Effect of Phase Margin Phase margin fM > 0 System stable (critical) undershoot We have to insure this parameter more large possible. t VO(t) 45° 70° 55° Harbin Institute of Technology, China Prof. Y. HU * July，2014 Two Stage Amplifier Design (1) Bias circuit design: For transistor M8: For transistor M9: and: We can determine IR, IO and IO2. M1 M2 M3 M4 M5 M7 M6 V+ IO C IR M8 M9 VSS VDD IO2 Harbin Institute of Technology, China Prof. Y. HU * July，2014 Two Stage Amplifier Design (2) Small signal gain: DC gain: AC gain: Vi = V+ - V- gmIVi gmIIV1 R2 R1 C1 C2 V1 CC instable Harbin Institute of Technology, China Prof. Y. HU * July，2014 Two Stage Amplifier Design (3) Compensation of frequency: A positive zero Two negative poles RE IM Z P1 P2 stable Harbin Institute of Technology, China Prof. Y. HU * July，2014 Two Stage Amplifier Design (4) Gain-bandwidth product: Choice of capacitor CC For a phase margin 60° instable Harbin Institute of Technology, China Prof. Y. HU * July，2014 Two Stage Amplifier Design (5) Elimination of zero: AV=1 CC M1 M2 M3 M4 M5 M7 M6 V+ IO CC M9 VSS VDD IO2 V- VO gmIVi gmIIV1 R2 R1 C1 C2 V1 Vi + - VO CC