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集成电路设 基于Verilog HDL的时序电路设计
赣南师院
物理与电子信息学院
集成电路课程设计报告书
基于Verilog HDL的时序电路设计
姓名：
班级：
学号：
指导老师： 陈 建 萍
时间： 2012年5月
目 录
摘要 ······················································································ 1
关键词 ·················································································· 1
1 引言···················································································· 2
2 时序逻辑电路······································································ 3
2.1 时序逻辑电路概述······························································ 3
2.2 同步时序逻辑电路的一般设计方法········································· 4
3 设计····················································································5
3.1 二进制计数器原理······························································ 5 3.1.1 同步二进制加法计数器的原理········································· 5
3.2 二进制计数器设计······························································ 6
3.2.1 四位二进制计数器的设计·············································· ··6
4 硬件描述语言VHDL设计及仿真·········································· ·8
4.1：用VHDL设计四位二进制加法计数器········································8
4.2：仿真················································································· 9
4.2.1仿真波形·········································································9
4.2.2时序分析·········································································10
5 体会与展望 ·········································································11
6 参考文献 ·············································································12
7 附件···················································································· 13
同步二进制加法计数器的设计与仿真
摘 要：本文首先介绍了同步时序逻辑电路一般设计步骤,然后在理解和掌握同步二进制计数器原理的基础上，采用传统的设计方法设计出了一个同步四位二进制加法计数器，并且运用软件对四位二进制计数器进行了仿真，根据仿真结果，对时序和波形进行了分析。最后采用VHDL语言设计了一个复杂的四位二进制加法计数器。
关键词：时序逻辑电路，同步二进制加法计数器，VHDL语言， 仿真
Design and simulation of synchronous binary carry counter
Abstract: this paper introduces the ordinary design method of
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