International Journal of Parallel Programming ( 2007) DOI 10.1007s10766-007-0041-6 Using F.pdfVIP

International Journal of Parallel Programming ( 2007) DOI 10.1007s10766-007-0041-6 Using F.pdf

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International Journal of Parallel Programming ( 2007) DOI 10.1007s10766-007-0041-6 Using F

DOI: 10.1007/s10766-007-0041-6 International Journal of Parallel Programming (? 2007) Using FORAYModels to Enable MPSoCMemory Optimizations Ilya Issenin,1,2 and Nikil Dutt1 Received November 16, 2006; accepted March 5, 2007 With the technology advances it becomes feasible to implement a large multiprocessor system on a single chip. In such Systems-on-Chip (SoCs), a significant portion of energy is spent in the memory subsystem. There are several approaches reducing this energy, including the ones at phys- ical, architecture and algorithmic levels. Classical approaches, including algorithmic and some architectural approaches, use static analysis and transformation of the application source code. However, often it is not possible to perform static analysis and optimization of a program’s memory access behavior unless the program is written in an easily analyzable form, e.g., free from pointer arithmetic. In this paper, we introduce the FORAY model of a program that allows aggressive analy- sis of the application’s memory behavior and enables such optimizations on arbitrary code which are not possible to apply otherwise. We then present FORAY-GEN: an automated profile-based approach for extraction of the FORAY model from the original program. We also outline our approach in applying FORAY-GEN for multiprocessor SoCs. We demonstrate how FORAY-GEN enhances applicability of other memory subsystem optimiza- tion approaches, resulting in an average of two times increase in the number of memory references that can be analyzed by existing static approaches. KEY WORDS: Embedded systems; memory optimizations; FORAY model; affine index expressions; scratch pad memory; MPSoC. 1. INTRODUCTION Advances in silicon technology have made it possible to integrate multiple processors and memories on a single multiprocessor SoC (MPSoC). Such 1Center for Embedded Computer System, School of Information and Computer Science, University of California at Irvine, Irvine, CA 92697, USA. E-mails:

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