Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development.pdfVIP

Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development Ken Eguro and Scott Hauck Department of Electrical Engineering University of Washington Seattle, WA 98195 USA {eguro, hauck}@ Abstract Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design problems that complicate their development. One source of these problems is that designers often opt to replace more universal, fine-grain logic elements with a specialized set of coarse-grain functional units to improve computation speed and reduce routing complexity. One issue this introduces is that it is not obvious how to simultaneously consider all applications in a domain and determine the most appropriate overall number and ratio of the different functional units. In this paper, we illustrate how this problem manifests itself during the development of an encryption-specialized FPGA architecture. We present three algorithms that solve this problem by balancing the hardware needs of the domain while considering performance and area requirements. We believe these concerns need to be addressed by future CAD tools in order to develop more sophisticated application- specialized reconfigurable devices. 1. Introduction While flexibility is an important feature of reconfigurable devices, conventional FPGAs are simply too generic to provide high performance in many situations. General-purpose reconfigurable devices, while well suited to small or irregular functions, typically suffer a stiff penalty when implementing wide and complex arithmetic operations. These types of functions need to be built from too many small logical resources and end up being spread across too general a routing structure to be efficient. However, if the range of applications that a device is intended for is known beforehand, a designer can specialize the logi