FPGA芯片中支持不同io电平基准.docxVIP

在fpga芯片中支持不同io电平标准 2008-06-06 15:15:39| 分类：  HYPERLINK /da_feng_chen@126/blog/ \l m=0t=1c=fks_080075085086081071083082074070085094087074085094086 \o FPGA AND DSP FPGA AND DSP | 标签： |字号大中小 订阅 I/O Banking Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages are externally supplied and connected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from separating each edge of the FPGA into two banks (see Figure 3). The pinout tables show the bank affiliation of each I/O (see Pinout Tables, Module 4). Each bank has multiple VCCO pins which must be connected to the same voltage. Voltage requirements are determined by the output standards in use. In the TQ144 and PQ208 packages, the eight banks have VCCO connected together. Thus, only one VCCO level is allowed in these packages, although different VREF values are allowed in each of the eight banks.Within a bank, standards may be mixed only if they use the same VCCO. [在spartan IIE的这两种封装中，每一个bank的io电引脚是连在一起的，而参考电平引脚是在不同的bank中是独立的，也就是说在所有bank中只能有一个io电平，每一个bank可以有自己的电平。在同一个bank中，可以支持不同的电平标准，但要求电平标准要相互兼容]Compatible standards are shown in Table 2.GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Note that VCCO is required for most output standards and for LVTTL,LVCMOS, and PCI inputs. VCCO Compatible Standards 3.3V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, LVPECL, GTL, GTL+ 2.5V SSTL2 I, SSTL2 II, LVCMOS2, LVDS, Bus LVDS, GTL, GTL+ 1.8V LVCMOS18, GTL, GTL+ 1.5V HSTL I, HSTL III, HSTL IV, GTL, GTL+ Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are automatically configured as inputs for the VREF voltage. About one in six of the I/O pins in the bank assume this role. VREF pins within a bank are interconnected internally and consequently only one VREF